1. Field of the Invention
The present invention relates to a data processor that can change over the address space depending on an operation mode and to, for example, a technique to be adequately applicable to a microcomputer.
2. Description of the Related Art
A certain microcomputer is loading a CPU (Central Processing Unit) having the operation modes in different address spaces as the access objects. For example, the Hitachi single chip microcomputer H8S/2148 and H8S/2144 series microcomputer manufactured by Hitachi, Ltd. have a couple of operation modes of the normal mode where the address space supported by CPU is 64 k-byte and the advanced mode of the 16 M-byte. Since difference of address space appears as a difference in the number of bits of the address information, the instruction code becomes short and program capacity can be reduced when the programming is made for the normal mode as in the case where the programming is performed for the advanced mode. Moreover, when the process is performed in the normal mode, the number of execution states can be reduced and the data processing operation is performed at a higher speed.
Since it is impossible to access to the address space exceeding 64 k-byte in the normal mode, there is a limitation that program and data capacity must be reduced. However, in some cases, it is difficult to satisfy the limitation of 64 k-byte for the tendency to realize high performance or complication of the microcomputer applied system. In this case, when the operation mode to operate in the 16 M-byte is selected, the merits of the operation mode to use the comparatively small address space such as 64 k-byte are decreased.
It is therefore an object of the present invention to provide a data processor that has relatively small access space of CPU and can improve convenience in the operation mode assuring higher efficiency of program.
It is another object of the present invention to provide a data processor that can alleviate limitation of program capacity while maintaining good execution efficiency of program with the comparatively small access space of CPU.
It is still another object of the present invention to provide a data processing system that can reduce the physical size of circuits and maintains good data processing efficiency in order to overcome the problems of high performance of program process and complication of the process.
The abovementioned objects and the other objects of the present invention will become apparent from description of the present specifications and accompanying drawings.
The typical inventions of the present invention will be explained briefly below.
[1] The data processor according to the first point of view of the present invention is capable of selectively setting a first or second mode and includes a processing section such as CPU, a memory section such as a built-in memory and a register or the like, and a transfer control section such as a direct memory access controller or a data transfer controller. This data processor is formed, for example, in one semiconductor chip. The data processor is capable, in the first mode, of accessing to the entire part of the memory by making access using an address signal that can be expressed with the number of the first bits and is also capable, in the second mode, of accessing to the first area as a part of the memory by making access using the address signal that can be expressed with the number of the second bits less than the number of first bits. The transfer control section is capable of executing the transfer control of information using the address signal that can be expressed with the number of first bits even in the second mode.
According to above explanation, even in the second operation mode, the data transfer control section can execute the data transfer control exceeding the address range that may be accessed with CPU. Namely, the transfer control section in the second mode controllably transfers the information to the other second areas from the first area of the memory in the address space that can be accessed with the address signal expressed with the number of first bits or controllably transfers the information stored in the second area to the first area.
Thereby, for example, even if a program or the like is generated exceeding the limit of program capacity for the accessible range of CPU in the second mode, when the program or the like exceeding such limitation is stored in the storage area other than the first area, CPU cannot make direct access to the program stored in the memory other than the first area. However, the transfer control section can make access to the program to transfer it to the first area, and CPU in the second mode can use the program transferred to the first area by accessing thereto. Accordingly, it is possible to alleviate the limitation of the program capacity while maintaining good execution efficiency of the program with the rather small access space of CPU.
[2] In the second mode, the transfer control section can select execution of transfer control of information using the address signal expressed with the number of first bits or execution of the transfer control of information using the address signal expressed with the number of second bits by further providing a control register means that can take the first or second condition. The transfer control section is allowed in the second mode to execute the first transfer control using the address signal expressed with the number of first bits in response to the first condition of the control register means and is also allowed to execute the second transfer control using the address signal expressed with the number of second bits in response to the second condition of the control register means.
For instance, in the second mode, the first transfer control enables the access to entire part of the memory, while the second transfer control enables the access to the first area of the memory.
When the second condition of the register means is selected, the CPU and the transfer control section access, in the second mode, the same address space to realize the operation mode similar to that of the data processor of the related art. Therefore, the existing operation program operated in such a condition is assured to execute in direct and compatibility for the data processor of the related art can be attained.
[3] To the first area, the transfer control information area wherein the transfer control information including the transfer source and destination address information for the transfer control by the transfer control section can be set in a plurality of sets with the data processor can be assigned, and the transfer control section may introduce the structure for reading transfer control information from the transfer control information area by receiving the drive instruction of the data transfer operation and to execute the transfer control depending on the transfer control information obtained by the reading operation.
When the data processor is provided with an external bus interface circuit to realize the bus interface with external circuit and the external circuit connected to the external bus interface circuit is assigned to the second area, the transfer control section in the second mode is capable of using CPU by transferring the data or program of external circuit not accessed from CPU to the first area of the memory.
When the data processor is provided with an input/output peripheral circuit that can interface with external circuits and this input/output peripheral circuit is provided with an I/O register arranged in the first area, the transfer control section transfers, in the second mode, the data of the second area no accessed from CPU to the I/O register in the first area and when CPU controls the input/output operation of the input/output peripheral circuit, the data in the second area can be communicated with the external circuit via the peripheral circuit.
[4] The memory can be formed by comprising ROM laid on the first and second areas, RAM included in the first area and the peripheral I/O register.
In this case, an electrically programmable flash memory may be used as ROM. When the program is stored in the flash memory, program correction for overcoming bug and update of program for version-up are enabled. When the update control is performed by the data processor, it is enough to store the update control program to be executed by the data processor in the second area of flash memory. At the time of updating, CPU in the second mode initially sets the transfer condition to the transfer control section and thereafter the transfer control section transfers the update control program in the second area and CPU controls update of the flash memory by executing such update control program.
[5] The data processing system from the second point of view of the present invention includes a data processor and a first external device. The data processor includes, for example, in the semiconductor chip, a data processor like CPU, a memory, a transfer control section and an external bus interface circuit connected to the first external device via the external bus and is capable of selectively setting the first mode or second mode. The data processor can access to the entire part of the memory by making access in the first mode using the address signal expressed with the number of first bits, while can access in the second mode to a part of the memory by making access using the address signal expressed with the number of second bits less than the number of first bits. The transfer control section is capable, even in the second mode, the transfer control of information using the address signal expressed with the number of first bits. The first external device connected to the external bus interface circuit is assigned to the second area other than the first area in the address space to be accessed using the address signal expressed with the number of first bits.
According to this data processing system, the transfer control section transfers, in the second mode, the data or program between the first external device not accessed from CPU and the first area of the memory.
The data processing system is also capable of providing a second external device. Namely, the data processor is further provided with the input/output peripheral circuit that can interface with external circuits, and the input/output peripheral circuit includes an I/O register arranged in the first area and the second external device for transmitting and receiving data to and from the I/O register is connected to the data processor. According to this structure, the transfer control section transfers, in the second mode, the data of the second area not accessed from CPU to the I/O register, and when CPU controls the input/output operation of the input/output peripheral circuit, the data in the second area can be communicated with the second external device via the input/output peripheral circuit. Moreover, in the second mode, the data can be transferred virtually between the first external device on the second area and the second external device in the second mode.
According to the data processing system explained above, it contributes to reduction of physical circuit scale in such a point that the memory of the data processor can be used effectively in the second mode and also can alleviate limitation of program capacity to realize high performance and provide a measure for complication, while maintaining good data processing efficiency by the second mode.
[6] The data processing system from the third point of view of the present invention includes the first data processor and second data processor that are respectively capable of making access to the memory and are connected to the common bus. The first data processor includes, for example, on the semiconductor chip, a data processor such as CPU, a memory, a transfer control section to selectively set the first mode or second mode. The data processor can access to the entire part of the memory by making access using the address signal expressed with the number of first bits in the first mode and also can access to the first area as a part of the memory by making access using the address signal expressed with the number of second bits that is less than the number of first bits in the second mode. The transfer control section can execute the transfer control of information using the address signal expressed with the number of first bits even in the second mode. In the second mode, the data processor assigns the third area included in the area (second area) other than the first area of the memory to the storage area of the second data processor in response to the first request from the second data processor and causes, in response to the second request from the second data processor, the data transfer control section to transfer the information supplied from the second data processor to the third area and also causes, in response to the third request from the second data processor, the data transfer control section to transfer the information to the second data processor from the third area.
The process responding to the first request is performed to obtain correspondence between the address of the memory built in the first data processor and the access address by the second data processor. Thereafter, when the second request such as the predetermined memory write access by the second data processor is issued, the data processor, for example, converts the write address to the address of the third area with reference to the information about correspondence explained above and then sets this address as one of the transfer condition to the transfer control section and causes the transfer control section to transfer the write data to the third area in the timing synchronized with the write access cycle of the second data processor. Moreover, when the third request such as the predetermined memory read access by the second data processor is issued, the data processor, for example, converts the read address to the address of the third area with reference to the information about correspondence explained above and causes the transfer control section to set this address as one of the transfer conditions and also causes the transfer control section to transfer the data to the second data processor from the third area in the timing synchronized with the read access cycle of the second data processor.
Thereby, in the second mode of the first data processor, the entire part or a part (third area) of the memory belonging to the second area as the non-access object memory by the built-in CPU of the first data processor can be used as the memory of the second data processor.
The information used by the first data processor is stored in the part other than the third area among the second area of the memory or the data used by the data processor can also be transferred to the first area from the part other than the third area of the second area of the memory.
In above explanation, the data processor converts the write address and read address to the address of the third area with reference to the correspondence relationship, but, on the contrary, it is also allowed that the second data processor converts the address to supply the address to the first data processor. In this case, it is enough that the transfer control section uses, in direct, the address signal supplied for the setting of the transfer control section.
The data processing system explained above can effectively use the memory built in the data processor in the second mode of the first data processor and moreover contributes to reduction of the physical circuit size of the data processing system in such a point that the memory built in the first data processor can be used in the second mode as the memory of the second data processor and also alleviates limitation of program capacity to realize higher performance of program process or take a measure for complication, while maintaining good data processing efficiency by the second mode.